(1) FIELD OF THE INVENTION
The present invention relates to methods of fabricating a dynamic random access memory having a high capacitance stacked capacitor.
(2) DESCRIPTION OF THE PRIOR ART
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capcitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, a decrease in storage capacitance, which results from the reduction in cell size, leads to draw backs, such as a lowering source/drain ratio and undesirable signal problems in terms of reliability. In order to achieve the desired higher leve of integration, it requires the technology to keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities in the fabrication of stacked capacitors are evident in T. Ema U.S. Pat. No. 4,910,566: S. Kimura et al U.S. Pat. No. 4,742,018 and T. Matsukawa U.S. Pat. No. 4,700,457. The publications "Are you ready for next-generation dynamic RAM chips?" by F. Masuoka pages 109-112, IEEE Spectrum, Nov. 1990, and T. Ema et al "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS" IEDM 1988 pages 592-595 describe the problems and possible types capacitor structures for future generations of dynamic RAMs. Another approach to achieve sufficient capacitance in high density memories is the use of a stacked trench capacitor cella s described in copending U.S. patent application of Wen doe Su entitled "FABRICATION OF MEMORY CELL WITH AN IMPROVED CAPACITOR" Ser. No. 07/568,945 filed Aug. 17, 1990.
It is well known that in the art of integrated circuit device manufacture, one of the primary goals is increasing the number of device that can be placed into a given unit space onthe semicondcutor chip. As the traditional fabrication process begin to approach the limit of reduction, considerable attention has been applied to forming device elements on over and above the wafer to take advantage of extra verstility of third dimension.
One of the successful vertically oriented integrated circuit devices is the stacked capacitor. Briefly, such a stacked capacitor is formed by forming the stacked capacitor structures laying over the gate electrode on active and fiedl oxide regions and diffusion region. The processing of such structures have become very complicated and require lithogrpahy and etching steps whch are not in step with the very small dimensions requird in the present and future state of the art. Although there has been much work done in accomplishing these small size devices and increased capacitance therein, there is still great need for devices with even greater capacitance for a give space in order to achieve even greater packing densities, and improve the DRAM products of the furture.